1. Field of the Invention
The present invention relates to a circuit implemented in complementary metal oxide semiconductor (CMOS) technology for providing a spare decoder circuit for random access memories and other semiconductor devices.
2. Description of the Prior Art
The use of spare components to replace defective components on semiconductor integrated circuit chips, generally referred to as "redundancy", has become increasingly utilized in recent years. The yield of good chips from a given wafer is strongly influenced by the size and number of defects that occur on the wafer. Such defects include defects in the silicon semiconductor crystal material that forms the substrate, as well as defects in oxide layers and conductors. Defects have become increasingly significant as the size of the individual components (that is the transistors, conductors, storage capacitors, resistors, and other components) becomes smaller relative to the size of the defects, and also as the overall area of the chip increases; both effects tend to increase the severity of the defect problem.
Fortunately, techniques have been developed to isolate defective portions of a circuit and substitute spare portions that have been included for that purpose. In particular, for the repair of memory chips wherein the memory cells are arranged in an array of rows and columns, techniques have been developed to substitute spare rows and columns; see for example, U.S. Pat. No. 4,228,528 co-assigned with the present invention. In that technique, fusible links are included to disconnect a defective row or column of memory cells, and means are provided for encoding the address of the disconnected portion into a spare row or column decoder, wherein the operation of the memory as viewed by an external user is substantially unaltered by the repair. The success of this technique in dealing with the defect problem has led to its incorporation in a large number of memories at the 64 kilobit level, and even a larger proportion at the 256 kilobit and 1 megabit levels.
To date, the incorporation of redundant rows and columns has been accomplished mainly in dynamic random access memories (DRAMs). Such memories typically utilize dynamic address decoders, so that relatively little average power is drawn during decoder operation, and virtually no power is drawn by the decoder during standby conditions. A typical programmable dynamic decoder is shown in FIG. 1. The fusible links are blown to encode the desired address into the decoder, so that a unique combination of the true and complement address lines produces a change in the voltage level at node 15. Redundant circuits have also been included in static type memories employing n-channel MOS (NMOS) technology, with a typical NMOS spare decoded circuit being shown in FIG. 2. The circuit includes a parallel string of NMOS transistors (T204-T209) to which true and complement address lines are connected. To program the decoder, one fusible link in each transistor pair (e.g., T204, T205 form a pair) is blown to disconnect the associated transistor. For example, in a decoder comprising two address line pairs (i.e., n=2) to encode the address A1 A2, the fusible links in the drain paths of T204 and T207 are blown. When address lines A1 and A2 are both in a low voltage state, node 21 goes to a high voltage state, due to conduction from positive voltage V.sub.cc through pull-up depletion type transistor T201. Any other address combination causes node 21 to be pulled to a low voltage state through T205 or T206. Transistors T202 and T203 provide that the decoder is able to respond to an address state only when the chip enable (CE) signal is high (and CE is low); otherwise, node 21 is pulled low through T203.
However, complementary metal oxide semiconductor (CMOS) technology is increasingly being used in memory (and other) circuits. A typical CMOS decoder circuit takes the form of a "tree decoder", wherein parallel p-channel MOS (PMOS) devices establish a high voltage state at the decoder output, and series NMOS devices are utilized to establish the low voltage level at the decoder output when the appropriate address is present.
To be suitable, a CMOS spare decoder circuit should not only be programmable, but also draw a minimum amount of current. In particular, CMOS devices have the potential for achieving very low standby current drains, since one transistor in a complementary pair can be off under static conditions. Hence, a spare decoder should preserve the very low standby current drain. Furthermore, it is desired that no link fusing be required if a spare decoder is not utilized to repair the chip.